Education

• Ph.D., The Ohio State University, 1989
• M.A.Sc., University of Ottawa, Canada, 1985
• B.E., University of Madras, India, 1982

Background

Dr. Sitaraman began at Tech in 1995 as an Assistant Professor. Prior, he was at IBM Corporation.

Research

• Computer-Aided Engineering and Design, Manufacturing, Micro & Nano Engineering, and Mechanics of Materials
• Fabrication, Testing, and Characterization of Micro- and Nano-Scale Structures, Physics-based Predictive Modeling and Reliable Design, Fatigue and Fracture, Rigid and Flexible Microsystems, Emerging Technologies

Dr. Sitaraman’s research focuses on fabrication, testing, and characterization of micro- and nano-scale structures, physics-based predictive modeling, reliable design, and development of innovative technologies as applied to rigid and flexible microsystems. For example, the research is developing fixtureless magnetic actuation test technique to determine interfacial fracture energy for thin-film structures.  In this test, an external electromagnet is used to debond the interface of interest under monotonic and fatigue loading conditions.  As no external fixturing is required to apply the load, it is easy to place the sample in a thermal/humidity chamber, debond the interface using an external electromagnet, and thus determine the interfacial fracture energy at different temperature/humidity conditions.

http://www.news.gatech.edu/2012/04/11/magnetic-testing-process-helps-ensure-reliability-microelectronic-devices

This magnetic actuation technique and other traditional interfacial fracture techniques such as double-cantilever beam test, four-point bend test, and brazil nut test, offer enormous insight into adhesion of dissimilar materials.  Such dissimilar materials are commonly used, for example, in rigid electronic systems, flexible electronic systems, photovoltaic systems, implantable medical devices, and others.  Fracture mechanics models and cohesive zone models are being developed and used to study various interfacial delamination failures.

Dr. Sitaraman’s research is also developing compliant micro-scale structures that can be used as electrical interconnects as well as thermal interface structures.  Various compliant structures having a single or multiple electrical paths have been fabricated, characterized, modeled, and tested to interconnect a chip to a substrate or a substrate to a board.  The compliance of the structures can mechanically isolate the chip from the substrate, and thus, reduce the stresses induced in the chip under thermal or mechanical loading compared to the stresses introduced in flip-chip solder bump interconnects with epoxy-based underfill materials. 

In addition to electrical interconnects, Dr. Sitaraman’s research group has explored electroplated copper nanowires as well as carbon nanotubes for thermal management and heat removal in microelectronic systems.  http://www.me.gatech.edu/featured_sitaramanwaviness

With the increasing focus on flexible electronic systems, Dr. Sitaraman’s group is exploring various printed materials, chip assemblies, mechanical test techniques, and physics-based models to study materials, devices, assemblies, and systems used in flexible hybrid electronic systems.  In addition to the challenges commonly seen in rigid electronics, flexible electronics requires additional fabrication, testing, characterization, and modeling approaches to meet the growing demands and emerging applications. 

With the continued push toward miniaturization, Dr. Sitaraman’s group is also studying 3D microsystems where chips are stacked on top of one another and are interconnected using through-silicon vias (TSVs) where typically copper is electroplated in silicon trenches.  Cracking of silicon dioxide, debonding of copper, copper pumping, copper microstructure changes under thermal excursion, and stacking and assembly of chips are some of the challenges associated with such 3D microsystems.  Through computational models, synchrotron x-ray diffraction measurements, and comprehensive experiments, Dr. Sitaraman’s group is studying the reliability issues of through-silicon vias.  In addition, Dr. Sitaraman’s group is exploring the use of glass substrates with through-glass vias for microsystem applications.

For details on the Computer-Aided Simulation of Packaging Reliability Lab, please visit www.caspar.gatech.edu

For details on Flexible Hybrid Electronics, please visit www.flex.gatech.edu