(Dr. Daniel Baldwin, advisor)

"Fundamentals of Area Array Solder Interconnect Yield"

Abstract

Demands for modern electronics that are small and combine high density with high speed, performance and reliability and can be brought to market quickly and inexpensively are driving the technologies of semiconductor, packaging and assembly. To meet these needs, a paradigm shift from peripheral interconnect to area array interconnect has become inevitable in electronic interconnects.

Nevertheless, some challenges must be overcome before the use of area array solder interconnects becomes routine. Of these challenges, the interconnect assembly yield is the critical issue that most significantly affects the total cost of the final product. Area array solder joints are difficult to inspect visually because solder joints are minuscule and covered by the chip. Consequently, the use of such joints may result in an increased number of interconnect defects getting through the inspection step only to become evident in subsequent process steps or in the testing of the finished product. Moreover, reworking of area array interconnects is difficult and costly, which means the economics of production favors prevention over detection and reworking of the product. The significance of interconnect yield becomes obvious as the demand for area array packages grows. Even a fractional interconnect failure rate has the potential to create huge financial losses.

The objective of this research is to suggest design guidelines to achieve, in the assembly process of area array solder interconnects, an interconnect yield defect rate as close to zero as possible. For that purpose, the parameters affecting interconnect yield are identified, a cause and effect analysis is performed and the relationships of design and process parameters to interconnect yield are modeled and verified experimentally. The results of these steps are used to develop process design rules to statistically achieve yield defect rate that is as close as possible to zero.