(Dr. Suresh Sitaraman, advisor)

"Process Modeling and Interfacial Delamination in a Peripheral Array Package"

Abstract

Interfacial delamination is one of the key failure modes in electronic packages that consist of dissimilar material systems. At fabrication and assembly temperatures, significant thermal stresses develop due to the Coefficient of Thermal Expansion (CTE) Mismatch among dissimilar material systems. The objectives of this research are to model the thermo-mechanical behavior of a Very Small Peripheral Array package (VSPA) fabrication process and examine the possibilities of interfacial delamination propagation.

As a first step, interfacial stresses were determined through creating 2D (plane strain and plane stress), pseudo-3D, and 3D models that would simulate the encapsulant cure process. Based on the comparison of stress results, an accurate yet computationally efficient scheme was identified to model the entire fabrication process. The results from the parametric material models could be used to select materials that would lower the potential of delamination in the package. In addition, the process models provide a true evolution of interfacial residual stress history which will be helpful for future reliability modeling.

The interfacial delamination was also studied from an interfacial fracture mechanics perspective. Two and three-dimensional models were constructed with cracks embedded in specific interfaces. The energy release rate was determined by employing Griffiths' energy balance and the Rybicki Crack Closure technique. The corresponding mode mixity was determined using the Crack Surface Displacement technique. These fracture mechanics parameters were compared with experimentally determined interfacial toughness data to determine the possibility of crack growth. A material parametric study was also completed using the cracked body models. The effect of plastic behavior on interfacial crack growth was also studied through J-Integral calculation.